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Job Details

Wireless ASIC Integration Engineer

Location
Cupertino, CA, United States

Posted on
Oct 23, 2020

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Wireless ASIC Integration Engineer
Santa Clara Valley (Cupertino)
California
United States
Hardware
Summary
Posted: Oct 22, 2020
Role Number: 200201644
Would you like to join Apple's growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Apple's extraordinary design and integration processes are made possible by top-notch integration engineers who own various blocks of the chip and coordinate with various teams to get all changes released to the database and production synthesized. This is a highly visible and critical role, which requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel. Want to join us and become part of this dynamic team?
Key Qualifications
This position requires a thorough knowledge of the ASIC design flow, FE and Design verification, synthesis, scripting and netlist generation.
WE'D LIKE YOU TO HAVE THE FOLLOWING BACKGROUND:
Preferably 10 years experience in ASIC design flow
Proven track record of high-performance designs in mass production for low power applications
Solid experience of RTL design and timing closure on large complex designs
EXPERTISE IN THE FOLLOWING WILL HELP YOU SUCCEED IN THIS ROLE:
SOC IP integration and RTL Design for performance, low area, and low power
FE production synthesis with DFT insertion
ASIC design flow and netlist flow checks - Lint, CDC, Logical Equivalence
UPF flow for defining power intent of chips with multiple power domains
Design interfacing to PD for floorplanning and timing closure
Strong communication skills are essential as you will collaborate with a lot of diverse groups within and outside the company
Self-starter, highly motivated, highly organized, and schedule driven are desired traits
Familiarity with DFT and backend related methodology and tools is a plus
Description
Own all aspects of development design for large SOC blocks including: internal and external IP integration, design of system bus and control bus logic for connectivity of IP blocks to main SOC infrastructure, ownership of the Integration Spec for the design project, integration and optimization of any memories and hard macros, run synthesis, netlist generation, and timing closure for the block. Work closely with Chip Architecture, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs. Develop and maintain methodology/flows/checks for your design. Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.
Education & Experience
BS required, MSEE desired
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
Requirements
See job description
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